Short Circuit Discharge and Over Current

Battery Management
1

Good day all, hope you are well, Finally some time to test and write back with some feed back on a project that might not be developed so much … but still for learning im trying my best to understand.
AS it stands ive learnt about the current sensor shunt and the voltage in relation to the parameters of the protect1 register .
Ive tried to Change the Rsns = 1 to 0 and this causes the bms not to discharge at all .
Secondly i am still wondering how to go about resolving the issue with regards to discharge over current and short circuit protection no protecting the system .
At this stage i have confirmed the registers only change when UV and OV for cells is present as a flag.
I did see the 8 defines in the Registers.h related to the Scd_thresh and wonder if this is where the error is being generated .
There is mention on github of the array for this being out of bounds .
I quote as reference .
"
for (int i = sizeof(SCD_threshold_setting)-1; i > 0; i–) {
if (conf->dis_sc_limit * conf->shunt_res_mOhm >= SCD_threshold_setting[i]) {
protect1.bits.SCD_THRESH = i;
break;
}
}
In above snippet, sizeof(SCD_threshold_setting) is expected to give the array length. But in reality, sizeof() returns the array size in bytes. And because @SCD_threshold_setting is composed of uint16_t elements, sizeof(SCD_threshold_setting) returns 2 bytes * array length."

would this cause the system not to function as it should ?
Both over current discharge and Short circuit Detection are non function .

how would i make use of a more sensitive Rsns = 0 instead of =1 ?
And would i be able to correct the code above function as it should . Please assist as i always did think this was a code issue more so then hardware .

2

So as matter of due course to ensure the hardware is correct ive used the following .
1 x 1 mOhm current sensing resistor .
According to the data sheet and the code we are using protect1.bits.RSNS = 1 which is the upper values of thresh .
Which means the lowest sensing voltage across pins SRP and SRN will be 44mv .
I have checked capacitor c4 on the board on both ends which will include voltage drop as well as losses and found that i get at least 55mv during the tests for both OCD and SCD .
I check the sys stat register and there is no change when printing the registers continously .
I have even gone as far as writting an instruction out of the loop in the library
protect1.bits.SCD_THRESH = 1 and or 7 with no change .
Im sure something is a miss but struggling to get to the bottom of it .
Skipping or missing out the array and setting the actual bits should work in theory as you write the register and then break in the code .
Verification was performed on both OCD and SCD with both unable to act based on the input values of SRP and SRN which i do find strange .
I will build another board incase this has some issue but from what i can tell at idle when on i get a 3mv across the pins and capacitor close to the AFE.

Any help would be greatly appreciated .

3

Hi @nismoboy34. Just realized that I also missed this post. Sorry for the late reply because of this.

I did not fully understand the question, as it’s a bit difficult to see which part of the code you are referring to. Could you please raise an issue on GitHub (in the firmware repository) where you reference the line of code which creates problems for you? In GitHub you can embed a link to the code section, making it easier to explain and understand an issue.